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ultra l ow noise , 150 ma cmos linear regulator adp150 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered tradem arks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 - 2010 analog devices, inc. all rights reserved. features ultra low noise: 9 v rms , independent of v out no additional noise bypass capacitor required stable with 1 f ceramic input and output capacitors maximum output current: 150 ma input voltage range: 2. 2 v to 5.5 v l ow q uiescent c urrent i gnd = 1 0 a with zero load low shutdown current: < 1 a low dropout voltage: 1 05 mv @ 150 ma load initial output voltage a ccuracy: 1 % up to 14 fi xed output voltage options: 1.8 v to 3.3 v psrr p erformance of 70 db at 1 0 khz current limit and thermal overload prot ecti on logic - controlled enable 5 - l ead tsot package 4 - ball , 0.8 mm 0.8 mm, 0.4 mm pitch wlcsp applications mobile phones digital camera and audio devices portable and battery - powered equipment post dc - to - dc regulation portable medical devices rf, pll, vco , a nd clock power supplies typical application circuit s 08343-001 nc = no connect 1 2 3 5 4 c out 1f c in 1f v out = 1.8v v in = 2.3v vout nc vin gnd en off on figure 1. 5 - lead tsot with fixed output voltage, 1.8 v vin vout 1 2 en gnd c out 1f c in 1f v out = 1.8v v in = 2.3v top view (not to scale) a b 08343-002 off on figure 2. 4 - ball wlcsp with fixed output voltage, 1.8 v general description the adp150 is an ultra low noise (9 v) , low dropout , linear regulator that operates from 2. 2 v to 5.5 v and provide s up to 150 ma of output current. the low 1 05 mv dropout volta ge at 150 ma load improves efficiency and allows operation over a wide input voltage range. u sing an innovative circuit topology, the adp150 achieves ultralow noise performance without the necessity of a n additional noise bypass capacitor , making it ideal for noise sensitive analog and rf applications . the adp150 also achieves ultralow noise perfo rmance without compromising psrr or line and load transient performance . the adp150 offers the best combination of ultralow noise and quiescent current consumption to maximize battery life in portable applications. the adp150 is specifically designed fo r stable operation with tiny 1 f 30% ceramic input and output capacitors to meet the requirements of high performance, space - constrained applications. the adp150 is available in 1 4 fixed output v oltage options, ranging from 1.8 v to 3.3 v. short - circuit a nd thermal overload protection circuits prevent damage in adverse conditions. the adp150 is available in tiny 5 - lead tsot and 4 - b all , 0. 4 mm pitch wlcsp packages for the smallest footprint solution to meet a variety of portable power applications.
adp150 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 recommended specifications: input and output capacitor .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 11 applications information .............................................................. 12 capacitor selection .................................................................... 12 undervoltage lockout ............................................................... 13 enable feature ............................................................................ 13 current limit and thermal overload protection ................. 13 therma l considerations ............................................................ 14 pcb layout considerations ...................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history 4/10 rev. 0 to rev. a changes to figure 21 ........................................................................ 9 10/0 9 revision 0 : initial version
adp150 rev. a | page 3 of 20 specifications v in = (v out + 0.4 v) or 2. 2 v , whichever is greater ; en = v in , i out = 1 0 m a , c in = c out = 1 f , t a = 25c , unless otherwise noted. table 1 . parameter symbol conditions min typ max unit input voltage range v in t j = ? 40c to +125c 2.2 5.5 v operating supply current i gnd i out = 0 a 10 a i out = 0 a, t j = ?40c to +125c 22 a i out = 100 a 20 a i out = 100 a, t j = ?40c to +125c 40 a i out = 10 ma 60 a i out = 10 ma, t j = ?40c to +125c 100 a i out = 150 ma 220 a i out = 150 ma, t j = ?40c to +125c 320 a shutdown curr ent i gnd - sd en = gnd 0.2 a en = gnd, t j = ?40c to +125c 1.0 a output voltage accuracy 5 - lead tsot v out i out = 10 ma ?1 +1 % 100 a < i out < 150 ma, v in = (v out + 0.4 v) to 5.5 v, t j = ?40c to +125c ?2.5 +1 .5 % 4 - ball wlcsp v out i out = 10 ma ?1 +1 % 100 a < i out < 150 ma, v in = (v out + 0.4 v) to 5.5 v, t j = ?40c to +125c ?2.0 +1 .5 % regulation line regulation ?v out / ?v in v in = (v out + 0.4 v) to 5.5 v, t j = ?40c to +125c ?0.05 +0.05 %/v load regulation 1 5 -l ead tsot ?v out / ?i out i out = 100 a to 150 ma 0.003 %/ma i out = 100 a to 150 ma, t j = ?40c to +125c 0.0075 %/ma 4 - ball wlcsp ?v out / ?i out i out = 100 a to 150 ma 0.002 %/ma i out = 100 a to 150 ma, t j = ?40c to +125c 0.006 %/ma dropout v o ltage 2 v dropout i out = 10 ma 10 mv i out = 10 ma, t j = ?40c to +125c 35 mv i out = 150 ma 105 mv i out = 150 ma, t j = ?40c to +125c 160 mv start - up time 3 t start - up v out = 3.3 v 150 s current limit threshold 4 i limit 190 260 400 ma undervoltage lockout uvlo input voltage rising uvlo rise t j = ?40c to +125c 1. 96 v input voltage falling uvlo fal l t j = ?40c to +125c 1.28 v hysteresis uvlo hys t j = ?40c to +125c 1 15 mv thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c en input en input logic high v ih 2.2 v v in 5.5 v 1.2 v en input logic low v il 2.2 v v in 5.5 v 0.4 v en input leakage current v i- leakage en = in or gnd 0. 001 a en = in or gnd, t j = ?40c to +125c 1 a output noise out noise 10 hz to 100 khz, v in = 5 v, v out = 3.3 v 9 v rms 10 hz to 100 khz, v in = 5 v, v out = 2.5 v 9 v rms 10 hz to 100 khz, v in = 5 v, v out = 1. 8 v 9 v rms
adp150 rev. a | page 4 of 20 parameter symbol conditions min typ max unit power supply rejectio n ratio (v in = v out + 0.5 v) psrr 10 khz, v in = 3.8 v, v out = 3.3 v, i out = 10 ma 70 db 10 khz, v in = 2.3 v, v out = 1.8 v, i out = 10 ma 70 db 100 khz, v in = 3.8 v, v out = 3.3 v, i out = 10 ma 55 db 100 khz, v in = 2.3 v, v out = 1.8 v, i out = 10 ma 55 db power supply rejection ratio (v in = v out + 1 v) 10 khz, v in = 4.3 v, v out = 3.3 v, i out = 10 ma 70 db 100 khz, v in = 4.3 v, v out = 3.3 v, i out = 10 ma 55 db 1 based on an end - point calculation using 1 ma and 15 0 ma loads. see figure 6 for t ypical load re gulation performance for loads less than 1 ma. 2 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. this applies only for output voltages above 2.2 v. 3 start - up time is defined as the time between the rising edges of en to v out being at 90 % of its nominal value. 4 current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. fo r example, the current lim it for a 3 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v or 2.7 v. recommended specific ations: input and output cap acitor table 2 . parameter symbol conditions min typ max unit input and output capacitor minimum input and output capacitance 1 c min t a = ?40c to +125c 0. 7 f capacitor esr r esr t a = ?40c to +125c 0 .001 0.2 ? 1 the minimum input and output capacitance should be greater than 0.7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r - type and x5r - type capacitors are recommended , and y5v and z5u capacitors are not recommended for use with a ny ldo.
adp150 rev. a | page 5 of 20 absolute maximum rat ings table 3 . parameter rating v in to gnd ? 0. 3 v to + 6 .5 v v out to gnd ? 0. 3 v to v in en to gnd ? 0. 3 v to + 6 .5 v storage temperature range ? 65c to +150c operating junction temperature range ? 40c to +125c operating ambient tempe rature range ?40c to +85 c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other c onditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually onl y, not in combination. the adp150 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor t hermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low printed circuit board ( pcb ) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ), and the junction - to - ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) by t j = t a + ( p d ja ) the j unction - to - ambient thermal resistance ( ja ) of the package is base d on modeling and a calculation using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja can vary, depending on p cb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 in ch 3 in ch circuit board . refer to jesd 51 - 7 and jesd 51 - 9 for detailed information on the bo ard construction. for additional information, see the an - 617 application note , microcsp ? wafer level chip scale package . jb is the junction - to - board thermal characterization parameter with units of c/w. jb of the package is based on modeling and a cal culation using a 4 - layer board. the jesd51 - 12, guidelines for reporting and using package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multipl e thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package , factors that make jb more useful in real - world applications. maximu m junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) by t j = t b + ( p d jb ) refer to jesd51 - 8 and jesd51 - 12 for more detailed information about jb . thermal resistance ja and jb are specified for the wors t - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jb unit 5 - lead tsot 170 43 c/w 4 - ball , 0. 4 mm pitch wlcsp 260 58 c/w esd caution
adp150 rev. a | page 6 of 20 pin configuration s and function descrip tions nc = no connect top view (not to scale) adp150 1 2 3 5 4 vin gnd en vout nc 08343-003 figure 3. 5- lead tsot pin configuration 1 2 a b top view (not to scale) vin vout en gnd 08343-004 figure 4. 4- ball wlcsp pin configuration table 5 . 5 - lead tsot pin function desc riptions pin no. mnemonic description 1 vin regulator input supply. bypass vin to gnd with a 1 f or greater capacitor. 2 gnd ground. 3 en enable input. drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic star tup, connect en to vin. 4 nc no connect. not connected internally. 5 vout regulated output voltage. bypass vout to gnd with a 1 f or greater capacitor. table 6 . 4 - ball wlcsp pin function descriptions pin no. mnemonic descriptio n a1 vin regulator input supply. bypass vin to gnd with a 1 f or greater capacitor. a2 vout regulated output voltage. bypass vout to gnd with a 1 f or greater capacitor. b1 en enable input. drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin. b2 gnd ground.
adp150 rev. a | page 7 of 20 typical performance characteristics v in = 3.7 v, v out = 3.3 v , i out = 1 ma , c in = c out = 1 f , t a = 25c, unless otherwise noted . 3.315 3.265 3.270 3.275 3.280 3.285 3.290 3.295 3.300 3.305 3.310 ?40 ?5 25 85 125 v out (v) junction temperature (c) 08343-005 i out = 0.1ma i out = 1ma i out = 10ma i out = 50ma i out = 100ma i out = 150ma figure 5 . output voltage (v out ) vs. junction temperature 3.298 3.290 3.291 3.292 3.293 3.294 3.295 3.296 3.297 0.01 1000 100 10 1 0.1 v out (v) i out (ma) 08343-006 figure 6 . output voltage (v out ) vs. load current (i out ) 3.300 3.288 3.290 3.292 3.294 3.296 3.298 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 v out (v) v in (v) 08343-007 i out = 0.1ma i out = 1ma i out = 10ma i out = 150ma i out = 50ma i out = 100ma figure 7 . output voltage (v out ) vs. input voltage (v in ) 300 250 200 150 100 50 0 ?40 ?5 25 85 125 ground current (a) junction temperature (c) 08343-008 i out = 0.1ma i out = 1ma i out = 10ma i out = 50ma i out = 100ma i out = 150ma figure 8 . gr ound current vs. junction temperature 08343-009 250 0 50 100 150 200 0.01 1000 100 10 1 0.1 ground current (a) i out (ma) figure 9 . ground current vs. load current (i out ) 250 200 150 100 50 0 3.5 5.5 5.3 5.1 4.9 4.7 4.5 4.3 4.1 3.9 3.7 ground current (a) v in (v) 08343-010 i out = 0.1ma i out = 1ma i out = 10ma i out = 50ma i out = 100ma i out = 150ma figure 10 . ground current vs. input voltage (v in )
adp150 rev. a | page 8 of 20 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?50 ?25 125 100 75 50 25 0 shutdown current (a) temperature (c) 08343-011 v in = 3.6v v in = 3.8v v in = 4.2v v in = 4.4v v in = 5.0v v in = 5.2v v in = 5.4v v in = 5.5v figure 11 . shutdown current v s. temperature at various input voltages 80 70 60 50 40 30 20 10 0 1 10 100 1000 dropout (ma) i out (ma) 08343-012 figure 12 . dropout voltage vs. load current (i load ) 3.35 3.30 3.25 3.20 3.15 3.10 3.00 3.05 3.05 3.10 3.45 3.40 3.35 3.30 3.25 3.20 3.15 v out (v) v in (v) 08343-013 i out = 10ma i out = 50ma i out = 100ma i out = 150ma figure 13 . output voltage (v out ) vs. input voltage (v in ) in dropout 700 600 500 400 300 200 100 0 3.05 3.10 3.45 3.40 3.35 3.30 3.25 3.20 3.15 ground current (a) v in (a) 08343-014 i out = 10ma i out = 50ma i out = 100ma i out = 150ma figure 14 . ground current vs. input voltage (v in ) in dropout ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i out = 100a i out = 1ma i out = 10ma i out = 100ma i out = 150ma 08343-015 v in = v out + 0.5v v ripple = 50mv c in = c out = 1f figure 15 . power supply rejection ratio (psrr) vs. frequency, v out = 1.8 v, v in = 2.3 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i out = 100a i out = 1ma i out = 10ma i out = 100ma i out = 150ma 08343-016 v in = v out + 0.5v v ripple = 50mv c in = c out = 1f figure 16 . power supply rejection ratio (psrr) vs. frequency, v out = 2.8 v, v in =3.3 v
adp150 rev. a | page 9 of 20 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) i out = 100a i out = 1ma i out = 10ma i out = 100ma i out = 150ma 08343-017 v in = v out + 0.5v v ripple = 50mv c in = c out = 1f figure 17 . power supply rejection ratio (psrr) vs. frequency, v out = 3.3 v, v in = 3.8 v ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) v out = 1.8v, i out = 100a v out = 2.8v, i out = 100a v out = 3.3v, i out = 100a v out = 1.8v, i out = 150ma v out = 2.8v, i out = 150ma v out = 3.3v, i out = 150ma 08343-018 v in = v out + 0.5v v ripple = 50mv c in = c out = 1f figure 18 . power supply rejection ratio (psrr) vs. frequency various ou tput voltages and load currents ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) v in = 3.8v, i out = 1ma v in = 4.3v, i out = 1ma v in = 5.3v, i out = 1ma v in = 3.8v, i out = 150ma v in = 4.3v, i out = 150ma v in = 5.3v, i out = 150ma 08343-019 v ripple = 50mv c in = c out = 1f figure 19 . power supply rejection ratio (psrr) vs. frequency with v arious headroom voltages (v in ? v out ), v out = 3.3 v 15 13 11 9 7 5 3 1 0.001 0.01 0.1 1 10 100 1k rms noise ( v) i out (ma) v out = 3.3v v out = 2.8v v out = 1.8v 08343-021 figure 20 . output rms noise vs. load current ( i out ) and output voltage (v out ), v in = 5 v, c out = 1 f 1 0.01 0.1 10 100 1k 10k 100k noise (v/ hz) frequency (hz) v out = 1.8v v out = 2.8v v out = 3.3v 08343-020 figure 21 . output noise spectrum, v in = 5 v, i load = 10 ma, c out = 1 f ch1 100ma ch2 50mv m40s a ch1 112ma t 117.560s 1 2 t 08343-022 i out 1ma to 150ma load step v out v in = 3.7v v out = 3.3v figure 22 . load transient response, c out = 1 f
adp150 rev. a | page 10 of 20 ch1 100ma ch2 50mv m40s a ch1 108ma t 118.000s 1 2 t 08343-023 i out 1ma to 150ma load step v out v in = 3.7v v out = 3.3v figure 23 . load transient response, c out = 4.7 f ch1 1.00v ch2 10mv m10s a ch1 4.60v t 29.60s 1 2 t 08343-024 v in 3.7v to 4.7v voltage step offset = 2.7v v out figure 24 . line transient response, c in , c out = 1 f, i load = 1ma ch1 1.00v ch2 10mv m10s a ch1 4.60v t 29.60s 1 2 t 08343-125 v in 3.7v to 4.7v voltage step offset = 2.7v v out figure 25 . line transient response, c in , c out =1 f, i load = 150 ma
adp150 rev. a | page 11 of 20 theory of operation the adp150 is a n ultra low noise, low quiescent current, low dropout linear regulator that operates from 2. 2 v to 5.5 v and can provide up to 150 ma of output current. drawing a low 22 0 a of quiescent current (typical) at full load makes the adp150 ideal for battery - operated portable equipment. shutdown current consumption is typically 2 00 na. using new innovative design techniques, the adp150 provides superior noise performance for noise sensitive analog and rf applications without the need for a noise bypass capacitor . the adp150 is also o ptimized for use with small 1 f ceramic capacitors . voltage reference short circuit, uvlo, and thermal protect shutdown r1 r2 vout vin gnd en 08343-025 figure 26 . internal block diagram internally, the adp150 consist s of a reference, an error amplifier, a feedback v oltage divider , and a pmos pass transistor. output current is delivered via the pmos pass device that is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the diffe rence. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass an d increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing le ss current to pass and decreasing the output voltage. the adp150 is available in 14 output voltage options , ranging from 1.8 v to 3. 3 v . the adp150 uses the en pin to enable and disable the v out pin under normal op erating conditions. when en is high, v out turns on, and when en is low, v out turns off. for automatic startup, en can be tied to v in.
adp150 rev. a | page 12 of 20 application s information capacitor selection output capacitor the adp150 is designed for operation with small, sp ace - saving ceramic capacitors but function s with most commonly used capacitors as long as care is taken with regard to the effective series resistance ( esr ) value. the esr of the output capaci tor affects the stabi lity of the ldo control loop . a minimum of 1 f capacitance with an esr of 1 ? or less is recommended to ensure the stability of the adp150 . the t ransient response to changes in load current is also a ffected by output capacitance . using a larger value of output capacitance improve s the transient re sponse of the adp150 to large changes in the load current. figure 27 and figure 28 show the transient responses for o utput capacitance values of 1 f and 4.7 f , respective ly . ch1 100ma ch2 50mv m1.0s a ch1 100ma t 716.000s 1 2 t 08343-126 i out 1ma to 150ma load step v out v in = 3.7v v out = 3.3v figure 27 . output transient response, c out = 1 f ch1 100ma ch2 50mv m1.0s a ch1 108ma t 240.000ns 1 2 t 08343-127 i out 1ma to 150ma load step v out v in = 3.7v v out = 3.3v figure 28 . output transient response, c out = 4.7 f input bypass capacitor connecting a 1 f capacitor from v in to gnd reduces the circuit sensitivi ty to the pcb layout, especially when long input traces or high source impedance is encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match the output capacitor . input and output capacitor properties any good quality ceramic capacitors can be used with the adp150 , as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and app lied voltage. c apacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions . x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended . y5v and z5u dielectrics a re not recommended , due to their poor temperature and dc bias characteristics. figure 29 depicts the capacitance vs . the voltage bias characteristic of a 0402, 1 f , 10 v, x5r capacitor . the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating . in general, a capacitor in a larger package or higher voltage rating exhibit s better stability . the temperature variation of the x5r dielectric is about 15% over the ? 40c to + 85 c temperature range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 capacitance (f) bias voltage (v) 08343-100 figure 29 . capacitance vs . voltage bias characteristic use equation 1 to determine the worst - case capacitance , accounting for capacitor variation over temper ature, component tolerance, and voltage. c eff = c bias (1 ? tempco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (t empco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and the c bias is 0.94 f at 1.8 v , as shown in figure 29. substituting these values in equation 1 yields c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage.
adp150 rev. a | page 13 of 20 to guarantee the perfo rmance of the adp150 , it is imperative that the effects of the dc bias, temperature, and toler ances on the behavior of the capacitors be evaluated for each . undervoltage lockout the adp150 ha s an internal undervoltage lockout circuit that disables all inpu ts and the output when the input voltage is less than approximately 2.0 v. this ensures that the adp150 inputs and output behave in a predictable manner during power - up. enable feature the adp150 use s the en pin to enable and disable the v out pin under nor mal operating conditions. as shown in figure 30, when a rising voltage on en crosses the active threshold, v out turns on. when a falling voltage on en crosses the inactive threshold, v out turns off. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v en v out 08343-101 figure 30 . typical en pin operation as shown in figure 30 , the en pin has hysteresis built in. this prevents on/off oscillations that can occur due to noise on the en pin as it passes through the threshold points. the en pin active/inactive thresholds are derived from the v in voltage ; t herefore, these thresholds vary with changing input vo ltage. figure 31 shows the typical en active/inactive thresholds when the inp ut voltage varies from 2. 2 v to 5.5 v. 1.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 typical threshold (v) v in (v) 5.5 5.3 4.8 4.3 3.8 3.3 2.8 2.3 rising falling 08343-102 figure 31 . typical en pin thresholds vs. input voltage (v in ) the adp150 u s e s an internal soft start to limit the inrush current when the output is enabled. the start - up time for the 3.3 v op tion is approximately 150 s from the time the en active threshold is crossed to when the output reaches 90% of its final value. as shown in figure 32 , the start - up time is dependent on the output voltage setting. 1 1 1 ch1 1v ch2 1v ch3 1v ch4 1v m40.0s a ch1 3.24v t 240.000ns 1 t en v out = 3.3v v out = 2.8v v out = 1.8v 08343-128 figure 32 . typical start - up time c urrent l imit and t hermal overload protection the adp150 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits . the adp150 is designed to limit current when the output load reaches 2 60 ma (typical). when the output load exceeds 2 6 0 ma, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included , which limit s the junction temperature to a ma ximum of 150c (typical) . under extreme conditions (that is, high ambient temperature and power dissipation) when the junction temperature starts to rise above 150c, the output is turned off , reduc ing the output current to zero . when the junction temperat ure drops below 135c, t he output is turned on again and the output current is restored to its nominal value . consi der the case where a hard short from v out to gnd occurs. at first , the adp150 limit s current so that only 2 6 0 ma is conducted into the short. if sel f - heating of the junction is great enough to cause its temperature to rise above 150c , thermal shutdown activ ate s , turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output t urn s on and conduct s 260 ma into the short, again caus ing the junction temperature to rise above 150c . this thermal oscillation between 135c and 150c cause s a current oscillation between 2 6 0 ma and 0 ma that continue s as long as the short remains at the output. current and thermal limit protections are intended to protect the device against accidenta l overload conditions. for reliable operation, device power dissipation must be externally limited so that the junction temperatures do not exceed 125c.
adp150 rev. a | page 14 of 20 th ermal considerations in most applications, the adp150 does not dissi pate much heat due to its high efficiency. however, in applications with high ambient temperature and high supply voltage to output voltage differential, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125c . when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the junction temper ature decrease s below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in equation 2. to guarantee reliable operation, the junction temperature of the adp150 must not exceed 125c. to ensure that the junction temperature stays below 125c , be aware of the parameters that contribute to the junction temperature changes. these parameters include ambient temperature , power dissipation in the power device, and thermal resistances between the junction and ambient air ( ja ). the ja nu mber is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pins to the pcb. table 7 shows typical ja values of the 5 - lead tsot and 4 - ball wlcsp packag e s for various pcb copper sizes. table 8 shows the typical jb value of the 5 - lead tsot and 4 - b a l l w l c s p. table 7 . typical ja values ja (c/w) copper size (mm 2 ) tsot wlcsp 0 1 170 260 5 0 152 159 100 146 157 300 134 153 500 131 151 1 device soldered to minimum size pin traces. table 8 . typical jb values jb (c/w) tsot wlcsp 42.8 58.4 use equation 2 to calculate the junction temperature. t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) where: i load is the load current. i gnd is the ground current. v in and v out are input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction tem perature equation simplifies to t j = t a + {[( v in ? v out ) i load ] ja } (3) as shown in the previous equation , for a given ambient temperature, input - to - output voltage differential, and continuous load current , there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 125c. figure 33 to figure 46 show the junction temperature calculations for t he different ambient temperatures, load currents, v in - to - v out differentials, and areas of pcb copper. 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-228 figure 33 . tsot, 500 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-229 figure 34 . tsot, 100 mm 2 of pcb copper, t a = 25c
adp150 rev. a | page 15 of 20 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-230 figure 35 . tsot, 0 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-231 figure 36 . tsot, 500 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-232 figure 37 . tsot, 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-233 figure 38 . tsot, 0 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) max junction temperature i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma 08343-248 figure 39 . tsot , 100 mm 2 of pcb copper , board temperature = 85c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-042 figure 40 . wlcsp, 500 mm 2 of pcb copper, t a = 25c
adp150 rev. a | page 16 of 20 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-043 figure 41 . wlcsp, 100 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) max junction temperature i load = 1ma i load = 10ma i load = 25ma i load = 100ma i load = 150ma i load = 50ma i load = 75ma 08343-044 figure 42 . wlcsp, 0 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-045 figure 43 . wlcsp, 500 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-046 figure 44 . wlcsp, 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma max junction temperature 08343-047 figure 45 . wlcsp, 0 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v in ? v out (v) junction temperature, t j (c) max junction temperature i load = 1ma i load = 10ma i load = 25ma i load = 50ma i load = 75ma i load = 100ma i load = 150ma 08343-049 figure 46 . wlcsp, 100 mm 2 of pcb copper, board temperature = 85c
adp150 rev. a | page 17 of 20 pcb layout consideration s heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp150 . however, as listed in table 7 , a point of diminishing returns is reached eventually , beyond which an increas e in the co pper size does not yield significant heat dissipation benefits . place t he input capacitor as close as possible to the v in and gnd pins. plac e t he output capacitor as close as possible to the v out and gnd pins . use of 0402 size or 0603 size capacitors and resistors achieve s the smallest possible footprint solution on boards where area is limited . 08343-147 figure 47 . example ts ot pcb layout 08343-148 figure 48 . example wlcsp pcb layout
adp150 rev. a | page 18 of 20 outline dimensions 100708-a * compliant to jedec standards mo-193-ab with the exception of package height and thickness. 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max * 1.00 max * 0.90 max 0.70 min 2.90 bsc 5 4 1 2 3 sea ting plane figure 49 . 5 - lead thin small outline transistor package [tsot] (uj - 5) dimensions show in millimeters 01 1509- a 0.050 nom coplanarity 0.800 0.760 sq 0.720 0.230 0.200 0.170 0.280 0.260 0.240 0.660 0.600 0.540 0.430 0.400 0.370 bot t om view (bal l side up) t op view (bal l side down) a 1 2 b sea ting plane 0.40 bal l pitch bal l a1 identifier figure 50 .4 - ball wafer level chip scale package [wlcsp] (cb - 4 - 3) dimensions show in millimeters
adp150 rev. a | page 19 of 20 ordering guide model 1 temperature range (t j ) output voltage (v) 2 package description package option branding adp150acbz - 1.8-r7 C 40c to +125c 1.8 4 - ball wa fer level chip scale package [wlcsp] cb -4 -3 36 adp150acbz - 2.5-r7 C 40c to +125c 2.5 4 - ball wafer level chip scale package [wlcsp] cb -4 -3 3v adp150acbz - 2.6-r7 C 40c to +125c 2.6 4 - ball wafer level chip scale package [wlcsp] cb -4 -3 63 adp150acbz - 2.75r7 C 40c to +125c 2.75 4 - ball wafer level chip scale package [wlcsp] cb -4 -3 3x adp150acbz - 2.8-r7 C 40c to +125c 2.8 4 - ball wafer level chip scale package [wlcsp] cb -4 -3 46 adp150acbz - 2.85r7 C 40c to +125c 2.85 4 - ball wafer level chip scale package [wlcsp ] cb -4 -3 3y adp150acbz - 3.0-r7 C 40c to +125c 3.0 4 - ball wafer level chip scale package [wlcsp] cb -4 -3 47 adp150acbz - 3.3-r7 C 40c to +125c 3.3 4 - ball wafer level chip scale package [wlcsp] cb -4 -3 48 adp150aujz - 1.8- r7 C 40c to +125c 1.8 5 - lead thin sma ll outline transistor package [tsot] uj -5 lds adp150aujz - 2.5- r7 C 40c to +125c 2.5 5 - lead thin small outline transistor package [tsot] uj -5 ldz adp150aujz - 2.8- r7 C 40c to +125c 2.8 5 - lead thin small outline transistor package [tsot] uj -5 le3 adp150auj z - 3.0- r7 C 40c to +125c 3.0 5 - lead thin small outline transistor package [tsot] uj -5 le2 adp150aujz - 3.3- r7 C 40c to +125c 3.3 5 - lead thin small outline transistor package [tsot] uj -5 lej adp150cb - 3.3- evalz 3.3 evaluation board with wlcsp package ad p150uj - 3.3- evalz 3.3 evaluation board with tsot package 1 z = rohs compliant part. 2 up to 14 fixed output voltage options from 1.8 v to 3.3 v are available. for additional voltage options, contact your local analog devices, inc, sales or distribution representative.
adp150 rev. a | page 20 of 20 notes ? 2009 - 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08343 - 0 - 4/10 (a)

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